This invention relates to a semiconductor integrated circuit device and a method of manufacturing the same. More particularly, the invention relates to the manufacture of MISFET (metal insulator semiconductor field effect transistor) having a so-called punch through stopper structure and also to a technique effective for application to the MISFET.
For the purpose of improving the drive ability of MISFET, the reduction in gate length of MISFET is now in progress. A shorter gate length of MISFET results in a shorter channel length, rendering the distance between a source and a drain shorter. This affords great influences of the source and drain characteristics on the electric field and potential distribution. One of the influences includes a short channel effect wherein when a channel length is at a certain level or below, the threshold voltage of MISFET abruptly lowers.
One of the phenomena caused by the short channel effect includes a lowering of the breakdown voltage between the source and drain of the MISFET. This is ascribed to a so-called punch through wherein a shorter gate length leads to the connection between a source depletion layer and a drain depletion layer, under which an electric current passes across the source and drain although any channel between the source and drain is not formed.
The punch through is divided into two categories including a shallow punch through that occurs in the vicinity of the surface of a semiconductor substrate and a deep punch through that occurs at a depth of about 0.1 μm or over from the surface of the semiconductor substrate. In order to suppress the occurrence of such punch throughs, a technique of providing a so-called punch through stopper (PTS) is known. The PTS structure includes a case wherein an impurity ion of a conduction type opposite to that of source-drain is ion implanted once thereby forming a pocket structure in the vicinity of a source-drain or LDD (lightly doped drain) structure, and another case wherein a similar impurity ion is implanted into the whole area of a channel region, thereby forming a PST structure wholly over the area.
The technique of suppressing the punch through by formation of the PTS structure is described, for example, in Japanese Laid-open Patent Application No. 2000-196079.